The present invention relates to a dual port memory device, and more particularly to the dual port memory device which commonly has a SAM (Serial Access Memory) port performing an input/output operation of serial data between a plurality of memory blocks and a RAM (Random Access Memory) port performing the input/output operation of random data.
Recently, the memory device has had large capacity. A method for reducing operative current by driving a plurality of memory blocks which are separated from a memory cell, has been developed. In such memory device, a specific memory block is enabled by an address signal applied from the out of the memory device. Further, a data access operation is performed via a sense amplifier and I/O lines provided to each of the memory blocks. Thereby, the more the memory device is subdivided into a plurality of memory blocks, the more the sense amplifier and the I/O lines associated with the input/output of data are increased and also occupy a wide region. This is more serious in the memory device having large capacity. Therefore, in order to solve this problem, an art that the memory blocks adjacent to each other have commonly one sense amplifier and the I/O lines is disclosed in the U.S. Pat. No. 5,014,246 issued in 1991.
The SAM and RAM ports should be provided to each of the memory blocks so that the dual port memory device which has the SAM port performing the data input/output operation in serial and the RAM port performing the data input/output operation in random, can be separately driven by the block. An art that the memory block has commonly the SAM port with the other memory block adjacent thereto is disclosed in the U.S. Pat. No. 4,984,214 issued in 1991.
As a construction view of a memory block of a dual port memory device according to the conventional art, FIG. 1 shows that the memory blocks adjacent to each other have commonly the SAM port.
Referring to FIG. 1, the two adjacent memory blocks 10 and 12 commonly include the SAM port 14 and a serial data I/O line and also have the RAM ports 16 and 18. The memory block 10 performs a random access operation through the RAM port 16 and performs a serial access operation through the SAM port 14. Further, the memory block 12 performs the random access operation through the RAM port 18 and performs the serial access operation through the SAM port 14 which is commonly included in the adjacent memory block 10. The dual port memory device shown in FIG. 1 is formed by the repeated construction of the two memory blocks which each have the RAM port and commonly have the SAM port. Therefore, the number of SAM ports is reduced by the half of the number of memory blocks.
However, the conventional dual port memory device shown in FIG. 1 has the RAM port which corresponds to the memory block one by one. Thereby, there aries a problem that the RAM port still occupies wide region, even if the number of SAM ports is reduced. This makes high integrated memory devices disadvantageous.